Update FENCE/FENCE.I decoding #138

mkurc-ant · 2023-11-22T13:12:59Z

This PR updates the instruction decoder so that it does not treat FENCE / FENCE.I with non-zero supplementary arguments as illegal. This behavior conforms to the spec in version "20190608-Base-Ratified" which VeeR is compatible with.

With that PR I also updated the instructions on how to re-generate instruction decoder equations.

Solves #128

github-actions · 2023-11-22T13:13:48Z

design/dec/el2_dec_decode_ctl.sv

@@ -1487,24 +1487,23 @@ end : cam_array

 endmodule // el2_dec_decode_ctl


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

endmodule // el2_dec_decode_ctl

endmodule // el2_dec_decode_ctl

github-actions · 2023-11-22T13:13:49Z

design/dec/el2_dec_decode_ctl.sv

-    &i[4]) | (i[2]) | (i[6]) | (!i[30]&i[29]&!i[24]&!i[23]&i[22]&i[21]
-    &i[20]&!i[5]&i[4]) | (!i[12]&!i[5]&i[4]);
+    &i[4]) | (i[6]) | (!i[30]&i[29]&!i[24]&!i[23]&i[22]&i[21]&i[20]&!i[5]
+    &i[4]) | (i[2]) | (!i[12]&!i[5]&i[4]);

 assign out.rs1 = (!i[13]&i[11]&!i[2]) | (!i[13]&i[10]&!i[2]) | (i[19]&i[13]&!i[2]) | (


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign out.rs1 = (!i[13]&i[11]&!i[2]) | (!i[13]&i[10]&!i[2]) | (i[19]&i[13]&!i[2]) | (

assign out.rs1 = (!i[13]&i[11]&!i[2]) | (!i[13]&i[10]&!i[2]) | (i[19]&i[13]&!i[2]) | (

github-actions · 2023-11-22T13:13:49Z

design/dec/el2_dec_decode_ctl.sv

@@ -1563,7 +1562,7 @@ assign out.sub = (i[30]&!i[14]&!i[12]&!i[6]&i[5]&i[4]&!i[2]) | (!i[29]&!i[25]&!i
 assign out.land = (!i[27]&!i[25]&i[14]&i[13]&i[12]&!i[6]&!i[2]) | (i[14]&i[13]&i[12]


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign out.land = (!i[27]&!i[25]&i[14]&i[13]&i[12]&!i[6]&!i[2]) | (i[14]&i[13]&i[12]

assign out.land = (!i[27]&!i[25]&i[14]&i[13]&i[12]&!i[6]&!i[2]) | (i[14]&i[13]&i[12]

github-actions · 2023-11-22T13:13:49Z

design/dec/el2_dec_decode_ctl.sv

@@ -1563,7 +1562,7 @@ assign out.sub = (i[30]&!i[14]&!i[12]&!i[6]&i[5]&i[4]&!i[2]) | (!i[29]&!i[25]&!i
 assign out.land = (!i[27]&!i[25]&i[14]&i[13]&i[12]&!i[6]&!i[2]) | (i[14]&i[13]&i[12]
    &!i[5]&!i[2]);

-assign out.lor = (!i[6]&i[3]) | (!i[29]&!i[27]&!i[25]&i[14]&i[13]&!i[12]&!i[6]&!i[2]) | (
+assign out.lor = (!i[29]&!i[27]&!i[25]&i[14]&i[13]&!i[12]&!i[6]&!i[2]) | (!i[6]&i[3]) | (


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign out.lor = (!i[29]&!i[27]&!i[25]&i[14]&i[13]&!i[12]&!i[6]&!i[2]) | (!i[6]&i[3]) | (

assign out.lor = (!i[29]&!i[27]&!i[25]&i[14]&i[13]&!i[12]&!i[6]&!i[2]) | (!i[6]&i[3]) | (

github-actions · 2023-11-22T13:13:49Z

design/dec/el2_dec_decode_ctl.sv

@@ -1624,7 +1623,7 @@ assign out.presync = (!i[5]&i[3]) | (!i[13]&i[7]&i[6]&i[4]) | (!i[13]&i[8]&i[6]&
    i[17]&i[13]&i[6]&i[4]) | (i[18]&i[13]&i[6]&i[4]) | (i[19]&i[13]&i[6]
    &i[4]);

-assign out.postsync = (i[12]&!i[5]&i[3]) | (!i[22]&!i[13]&!i[12]&i[6]&i[4]) | (
+assign out.postsync = (!i[22]&!i[13]&!i[12]&i[6]&i[4]) | (i[12]&!i[5]&i[3]) | (


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign out.postsync = (!i[22]&!i[13]&!i[12]&i[6]&i[4]) | (i[12]&!i[5]&i[3]) | (

assign out.postsync = (!i[22]&!i[13]&!i[12]&i[6]&i[4]) | (i[12]&!i[5]&i[3]) | (

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

github-actions · 2023-11-22T13:39:54Z

design/dec/el2_dec_decode_ctl.sv

+// To generate instruction legality check equation do:
+//  1) coredecode -in decode -legal > legal.e
+//  2) espresso -Dso -oeqntott < legal.e | addassign -pre out. > legal
+//  3) copy-paste assignment from the file "legal" and replace the one below.

 module el2_dec_dec_ctl
 import el2_pkg::*;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

import el2_pkg::*;

import el2_pkg::*;

github-actions · 2023-11-22T13:39:54Z

design/dec/el2_dec_decode_ctl.sv

+  input logic [31:0] inst,
+  output el2_dec_pkt_t out


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input logic [31:0] inst,

output el2_dec_pkt_t out

input logic [31:0] inst,

output el2_dec_pkt_t out

github-actions · 2023-11-22T13:39:54Z

design/dec/el2_dec_decode_ctl.sv

    !i[13]&i[9]&!i[2]) | (i[18]&i[13]&!i[2]) | (!i[13]&i[8]&!i[2]) | (
    i[17]&i[13]&!i[2]) | (!i[13]&i[7]&!i[2]) | (i[16]&i[13]&!i[2]) | (
    i[15]&i[13]&!i[2]) | (!i[4]&!i[2]) | (!i[14]&!i[13]&i[6]&!i[3]) | (
    !i[6]&!i[2]);

-assign out.rs2 = (i[5]&!i[4]&!i[2]) | (!i[6]&i[5]&!i[2]);
+  assign out.rs2 = (i[5]&!i[4]&!i[2]) | (!i[6]&i[5]&!i[2]);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign out.rs2 = (i[5]&!i[4]&!i[2]) | (!i[6]&i[5]&!i[2]);

assign out.rs2 = (i[5] & !i[4] & !i[2]) | (!i[6] & i[5] & !i[2]);

github-actions · 2023-11-22T13:39:54Z

design/dec/el2_dec_decode_ctl.sv

    &i[6]&i[4]) | (!i[12]&!i[5]&i[4]&!i[2]);

-assign out.rd = (!i[5]&!i[2]) | (i[5]&i[2]) | (i[4]);
+  assign out.rd = (!i[5]&!i[2]) | (i[5]&i[2]) | (i[4]);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign out.rd = (!i[5]&!i[2]) | (i[5]&i[2]) | (i[4]);

assign out.rd = (!i[5] & !i[2]) | (i[5] & i[2]) | (i[4]);

github-actions · 2023-11-22T13:39:55Z

design/dec/el2_dec_decode_ctl.sv

    &!i[5]&i[4]&!i[2]) | (i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);

-assign out.imm20 = (i[5]&i[3]) | (i[4]&i[2]);
+  assign out.imm20 = (i[5]&i[3]) | (i[4]&i[2]);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign out.imm20 = (i[5]&i[3]) | (i[4]&i[2]);

assign out.imm20 = (i[5] & i[3]) | (i[4] & i[2]);

github-actions · 2023-11-22T13:39:57Z

design/dec/el2_dec_decode_ctl.sv

    !i[27]&i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);

-assign out.rs2_sign = (!i[27]&i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
+  assign out.rs2_sign = (!i[27]&i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign out.rs2_sign = (!i[27]&i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);

assign out.rs2_sign = (!i[27] & i[25] & !i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);

github-actions · 2023-11-22T13:39:58Z

design/dec/el2_dec_decode_ctl.sv


-assign out.low = (i[25]&!i[14]&!i[13]&!i[12]&i[5]&i[4]&!i[2]);
+  assign out.low = (i[25]&!i[14]&!i[13]&!i[12]&i[5]&i[4]&!i[2]);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign out.low = (i[25]&!i[14]&!i[13]&!i[12]&i[5]&i[4]&!i[2]);

assign out.low = (i[25] & !i[14] & !i[13] & !i[12] & i[5] & i[4] & !i[2]);

github-actions · 2023-11-22T13:39:58Z

design/dec/el2_dec_decode_ctl.sv


-assign out.div = (!i[27]&i[25]&i[14]&!i[6]&i[5]&!i[2]);
+  assign out.div = (!i[27]&i[25]&i[14]&!i[6]&i[5]&!i[2]);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign out.div = (!i[27]&i[25]&i[14]&!i[6]&i[5]&!i[2]);

assign out.div = (!i[27] & i[25] & i[14] & !i[6] & i[5] & !i[2]);

github-actions · 2023-11-22T13:39:58Z

design/dec/el2_dec_decode_ctl.sv


-assign out.rem = (!i[27]&i[25]&i[14]&i[13]&!i[6]&i[5]&!i[2]);
+  assign out.rem = (!i[27]&i[25]&i[14]&i[13]&!i[6]&i[5]&!i[2]);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign out.rem = (!i[27]&i[25]&i[14]&i[13]&!i[6]&i[5]&!i[2]);

assign out.rem = (!i[27] & i[25] & i[14] & i[13] & !i[6] & i[5] & !i[2]);

github-actions · 2023-11-22T13:39:58Z

design/dec/el2_dec_decode_ctl.sv


-assign out.fence = (!i[5]&i[3]);
+  assign out.fence = (!i[5]&i[3]);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign out.fence = (!i[5]&i[3]);

assign out.fence = (!i[5] & i[3]);

Internal-tag: [#51652] Signed-off-by: Maciej Kurc <[email protected]>

github-actions · 2023-12-06T10:39:09Z

Links to coverage and verification reports for this PR (#138) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

tmichalak · 2023-12-07T09:13:55Z

LGTM

github-actions bot reviewed Nov 22, 2023

View reviewed changes

mkurc-ant mentioned this pull request Nov 22, 2023

[Bug report] fence.i may cause the CPU to hang under some conditions #128

Closed

github-actions bot reviewed Nov 22, 2023

View reviewed changes

mkurc-ant force-pushed the mkurc/fix-fence branch from 97b334d to d5f91a0 Compare November 22, 2023 14:01

mkurc-ant added 2 commits December 6, 2023 10:12

Update FENCE/FENCE.I decoding to ignore unused arguments

afca5e4

Internal-tag: [#51652] Signed-off-by: Maciej Kurc <[email protected]>

Fix linter errors

0b0a4dd

Internal-tag: [#51652] Signed-off-by: Maciej Kurc <[email protected]>

mkurc-ant force-pushed the mkurc/fix-fence branch from d5f91a0 to 0b0a4dd Compare December 6, 2023 09:12

tmichalak merged commit 61c88e1 into chipsalliance:main Dec 7, 2023
148 checks passed

tmichalak deleted the mkurc/fix-fence branch October 22, 2024 13:29

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Update FENCE/FENCE.I decoding #138

Update FENCE/FENCE.I decoding #138

mkurc-ant commented Nov 22, 2023

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github-actions bot commented Dec 6, 2023

tmichalak commented Dec 7, 2023

		@@ -1487,24 +1487,23 @@ end : cam_array

		endmodule // el2_dec_decode_ctl

	assign out.rs1 = (!i[13]&i[11]&!i[2]) \| (!i[13]&i[10]&!i[2]) \| (i[19]&i[13]&!i[2]) \| (
	assign out.rs1 = (!i[13]&i[11]&!i[2]) \| (!i[13]&i[10]&!i[2]) \| (i[19]&i[13]&!i[2]) \| (

		@@ -1563,7 +1562,7 @@ assign out.sub = (i[30]&!i[14]&!i[12]&!i[6]&i[5]&i[4]&!i[2]) \| (!i[29]&!i[25]&!i
		assign out.land = (!i[27]&!i[25]&i[14]&i[13]&i[12]&!i[6]&!i[2]) \| (i[14]&i[13]&i[12]

	assign out.lor = (!i[29]&!i[27]&!i[25]&i[14]&i[13]&!i[12]&!i[6]&!i[2]) \| (!i[6]&i[3]) \| (
	assign out.lor = (!i[29]&!i[27]&!i[25]&i[14]&i[13]&!i[12]&!i[6]&!i[2]) \| (!i[6]&i[3]) \| (

	assign out.postsync = (!i[22]&!i[13]&!i[12]&i[6]&i[4]) \| (i[12]&!i[5]&i[3]) \| (
	assign out.postsync = (!i[22]&!i[13]&!i[12]&i[6]&i[4]) \| (i[12]&!i[5]&i[3]) \| (

	assign out.rs2 = (i[5]&!i[4]&!i[2]) \| (!i[6]&i[5]&!i[2]);
	assign out.rs2 = (i[5] & !i[4] & !i[2]) \| (!i[6] & i[5] & !i[2]);

	assign out.rd = (!i[5]&!i[2]) \| (i[5]&i[2]) \| (i[4]);
	assign out.rd = (!i[5] & !i[2]) \| (i[5] & i[2]) \| (i[4]);

	assign out.imm20 = (i[5]&i[3]) \| (i[4]&i[2]);
	assign out.imm20 = (i[5] & i[3]) \| (i[4] & i[2]);

	assign out.rs2_sign = (!i[27]&i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
	assign out.rs2_sign = (!i[27] & i[25] & !i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);


		assign out.low = (i[25]&!i[14]&!i[13]&!i[12]&i[5]&i[4]&!i[2]);
		assign out.low = (i[25]&!i[14]&!i[13]&!i[12]&i[5]&i[4]&!i[2]);

	assign out.low = (i[25]&!i[14]&!i[13]&!i[12]&i[5]&i[4]&!i[2]);
	assign out.low = (i[25] & !i[14] & !i[13] & !i[12] & i[5] & i[4] & !i[2]);


		assign out.div = (!i[27]&i[25]&i[14]&!i[6]&i[5]&!i[2]);
		assign out.div = (!i[27]&i[25]&i[14]&!i[6]&i[5]&!i[2]);

	assign out.div = (!i[27]&i[25]&i[14]&!i[6]&i[5]&!i[2]);
	assign out.div = (!i[27] & i[25] & i[14] & !i[6] & i[5] & !i[2]);


		assign out.rem = (!i[27]&i[25]&i[14]&i[13]&!i[6]&i[5]&!i[2]);
		assign out.rem = (!i[27]&i[25]&i[14]&i[13]&!i[6]&i[5]&!i[2]);

	assign out.rem = (!i[27]&i[25]&i[14]&i[13]&!i[6]&i[5]&!i[2]);
	assign out.rem = (!i[27] & i[25] & i[14] & i[13] & !i[6] & i[5] & !i[2]);


		assign out.fence = (!i[5]&i[3]);
		assign out.fence = (!i[5]&i[3]);

	assign out.fence = (!i[5]&i[3]);
	assign out.fence = (!i[5] & i[3]);

Update FENCE/FENCE.I decoding #138

Update FENCE/FENCE.I decoding #138

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github-actions bot commented Dec 6, 2023

tmichalak commented Dec 7, 2023